1. Field of the Invention
This technology relates to a sense circuit.
2. Description of Related Art
In a program operation flow which includes program and program verify phases, the Fast Program Write (FPW) algorithm is accompanied by a FPW program verify algorithm. The FPW algorithm can result in memory cells that nearly pass program verify, but ultimately fail. For more accurate judgment of whether a memory cell has been programmed successfully, the FPW algorithm increases the number of program verify cycles when a programmed memory cell fails program verify. Thus the FPW program operation flow comes with a serious speed penalty. In some cases, the number of program verify cycles is as much as doubled in response to a program verify failure.
One approach to address failures in program verify, is to decrease the step voltage during programming such as Incremental Step Pulse Programming (ISPP). However, although a decreased programming step voltage improves programming accuracy, the decreased programming step voltage also results in a serious speed penalty.
It would be desirable to improve the results of the program operation flow without an accompanying speed penalty.